
main.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <main>:
   0:	b480      	push	{r7}
   2:	b083      	sub	sp, #12
   4:	af00      	add	r7, sp, #0
   6:	4b11      	ldr	r3, [pc, #68]	; (4c <main+0x4c>)
   8:	681b      	ldr	r3, [r3, #0]
   a:	4a10      	ldr	r2, [pc, #64]	; (4c <main+0x4c>)
   c:	f043 0301 	orr.w	r3, r3, #1
  10:	6013      	str	r3, [r2, #0]
  12:	4b0f      	ldr	r3, [pc, #60]	; (50 <main+0x50>)
  14:	681b      	ldr	r3, [r3, #0]
  16:	4a0e      	ldr	r2, [pc, #56]	; (50 <main+0x50>)
  18:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
  1c:	6013      	str	r3, [r2, #0]
  1e:	4b0c      	ldr	r3, [pc, #48]	; (50 <main+0x50>)
  20:	681b      	ldr	r3, [r3, #0]
  22:	4a0b      	ldr	r2, [pc, #44]	; (50 <main+0x50>)
  24:	f423 6300 	bic.w	r3, r3, #2048	; 0x800
  28:	6013      	str	r3, [r2, #0]
  2a:	4b0a      	ldr	r3, [pc, #40]	; (54 <main+0x54>)
  2c:	681b      	ldr	r3, [r3, #0]
  2e:	4a09      	ldr	r2, [pc, #36]	; (54 <main+0x54>)
  30:	f083 0320 	eor.w	r3, r3, #32
  34:	6013      	str	r3, [r2, #0]
  36:	2300      	movs	r3, #0
  38:	607b      	str	r3, [r7, #4]
  3a:	e002      	b.n	42 <main+0x42>
  3c:	687b      	ldr	r3, [r7, #4]
  3e:	3301      	adds	r3, #1
  40:	607b      	str	r3, [r7, #4]
  42:	687b      	ldr	r3, [r7, #4]
  44:	4a04      	ldr	r2, [pc, #16]	; (58 <main+0x58>)
  46:	4293      	cmp	r3, r2
  48:	ddf8      	ble.n	3c <main+0x3c>
  4a:	e7ee      	b.n	2a <main+0x2a>
  4c:	40023830 	andmi	r3, r2, r0, lsr r8
  50:	40020000 	andmi	r0, r2, r0
  54:	40020014 	andmi	r0, r2, r4, lsl r0
  58:	000dbb9f 	muleq	sp, pc, fp	; <UNPREDICTABLE>

Disassembly of section .comment:

00000000 <.comment>:
   0:	43434700 	movtmi	r4, #14080	; 0x3700
   4:	4728203a 			; <UNDEFINED> instruction: 0x4728203a
   8:	4120554e 			; <UNDEFINED> instruction: 0x4120554e
   c:	45206d72 	strmi	r6, [r0, #-3442]!	; 0xfffff28e
  10:	6465626d 	strbtvs	r6, [r5], #-621	; 0xfffffd93
  14:	20646564 	rsbcs	r6, r4, r4, ror #10
  18:	6c6f6f54 	stclvs	15, cr6, [pc], #-336	; fffffed0 <main+0xfffffed0>
  1c:	69616863 	stmdbvs	r1!, {r0, r1, r5, r6, fp, sp, lr}^
  20:	3031206e 	eorscc	r2, r1, lr, rrx
  24:	322d332e 	eorcc	r3, sp, #-1207959552	; 0xb8000000
  28:	2e313230 	mrccs	2, 1, r3, cr1, cr0, {1}
  2c:	20293730 	eorcs	r3, r9, r0, lsr r7
  30:	332e3031 			; <UNDEFINED> instruction: 0x332e3031
  34:	3220312e 	eorcc	r3, r0, #-2147483637	; 0x8000000b
  38:	30313230 	eorscc	r3, r1, r0, lsr r2
  3c:	20313236 	eorscs	r3, r1, r6, lsr r2
  40:	6c657228 	sfmvs	f7, 2, [r5], #-160	; 0xffffff60
  44:	65736165 	ldrbvs	r6, [r3, #-357]!	; 0xfffffe9b
  48:	Address 0x00000048 is out of bounds.


Disassembly of section .ARM.attributes:

00000000 <.ARM.attributes>:
   0:	00002d41 	andeq	r2, r0, r1, asr #26
   4:	61656100 	cmnvs	r5, r0, lsl #2
   8:	01006962 	tsteq	r0, r2, ror #18
   c:	00000023 	andeq	r0, r0, r3, lsr #32
  10:	2d453705 	stclcs	7, cr3, [r5, #-20]	; 0xffffffec
  14:	0d06004d 	stceq	0, cr0, [r6, #-308]	; 0xfffffecc
  18:	02094d07 	andeq	r4, r9, #448	; 0x1c0
  1c:	01140412 	tsteq	r4, r2, lsl r4
  20:	03170115 	tsteq	r7, #1073741829	; 0x40000005
  24:	01190118 	tsteq	r9, r8, lsl r1
  28:	061e011a 			; <UNDEFINED> instruction: 0x061e011a
  2c:	Address 0x0000002c is out of bounds.

